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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 62: Regional Clock Switching Characteristics (BUFR) (Cont’d)
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
T BRDO_O
Propagation delay from CLR to O
0.69
0.74
0.80
1.12
ns
Maximum Frequency
F MAX (1)
Regional clock tree (BUFR)
500
420
300
300
MHz
Notes:
1.
The maximum input frequency to the BUFR is the BUFIO F MAX frequency.
Table 63: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
T BHCKO_O
T BHCCK_CE /T BHCKC_CE
BUFH delay from I to O
CE pin Setup and Hold
0.10
0.04/
0.04
0.11
0.04/
0.04
0.13
0.05/
0.05
0.15
0.04/
0.04
ns
ns
Maximum Frequency
F MAX
Horizontal clock buffer (BUFH)
800
750
700
667
MHz
MMCM Switching Characteristics
Table 64: MMCM Specification
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
F INMAX
F INMIN
Maximum Input Clock Frequency (1)
Minimum Input Clock Frequency
800
10
750
10
700
10
700
10
MHz
MHz
F INJITTER
Maximum Input Clock Period Jitter
< 20% of clock input period or 1 ns Max
F INDUTY (2)
Allowable Input Duty Cycle: 10—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
25/75
30/70
35/65
40/60
45/55
%
%
%
%
%
F MIN_PSCLK
F MAX_PSCLK
F VCOMIN
F VCOMAX
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
Maximum MMCM VCO Frequency
0.01
550
600
1600
0.01
500
600
1440
0.01
450
600
1200
0.01
450
600
1200
MHz
MHz
MHz
MHz
F BANDWIDTH
Low MMCM Bandwidth at
High MMCM Bandwidth at
Typical (3)
Typical (3)
1.00
4.00
1.00
4.00
1.00
4.00
1.00
4.00
MHz
MHz
T STATPHAOFFSET
Static Phase Offset of the MMCM
Outputs (4)
0.12
0.12
0.12
0.12
ns
T OUTJITTER
MMCM Output
Jitter (5)
T OUTDUTY
MMCM Output Clock Duty Cycle
Precision (6)
0.15
0.20
0.20
0.20
ns
T LOCKMAX
F OUTMAX
MMCM Maximum Lock Time
MMCM Maximum Output Frequency
100
800
100
750
100
700
100
700
μs
MHz
F OUTMIN
MMCM Minimum Output
Frequency (7)(8)
4.69
4.69
4.69
4.69
MHz
T EXTFDVAR
External Clock Feedback Variation
< 20% of clock input period or 1 ns Max
DS152 (v3.6) March 18, 2014
Product Specification
52
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